The present invention relates generally to an input power supply for an integrated circuit and more particularly, to a power switch for preventing a false electrostatic discharge (ESD) trigger in an input/output pad of an integrated circuit.
Recently, there has been a lot of development in the field of Integrated Circuit (IC) devices. The rapidly decreasing size of these devices has led to the development of System on Chip (SoC) designs. A SoC can be referred to as a system in which all the components of an electronic device are integrated on a single IC. These SoC designs can be packaged in various ways, where each package is designed for a particular function. This helps reduce cost as the same die can be sold in different packages, some with limited pin count.
Low power SoC designs as well as multi-package options have led to switchable supply requirements becoming an important consideration. Traditionally, the nonfunctional I/O segments of an IC were left unpowered. However, this resulted in significant loss of desired functionality of the device. Further, powering each I/O segment in an IC is avoided due to limitations in pin count and other packaging constraints.
Power switches may be used for providing power to the I/O segment, but these power switches operate on a resistive start-up, which is not ideal for use as I/O supply due to a fast ramp rate of the output potential. The fast ramp rate can activate a false trigger of the electrostatic discharge circuitry present within the pads of the IC, resulting in a large power loss. FIGS. 1A, 1B AND 1C illustrate the behavior of a traditional power switch, in particular the voltage-time characteristics of an input supply, an output supply and a control signal. The input signal, as illustrated in FIG. 1A, is a ramp signal that starts at time t1 and attains a maximum value at time t2. At time t3, the input reaches a threshold value Vth, which triggers the power switch. When triggered, the power switch produces the output signal at time t4 as shown in FIG. 1B. A control signal, as illustrated in FIG. 1C, is activated externally to determine the threshold Vth. The output signal generated by the power switch ramps up at a fast rate to attain its maximum value at t5. The short duration (t4-t5) of the ramp up of output voltage can cause a false trigger due to ESD. The size of a power switch may be reduced to prevent the false trigger, but this reduces the drive capability and cause the output to drop when in operation.
It would be advantageous to have a switch that provides an output supply potential to the IC and prevents generation of a false trigger due to electrostatics discharge. It also would be advantageous if the power switch has good drive capability to ensure that the output does not drop during operation.